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Asynchronous FPGA risksThe worst case timing margin of a synchronous design implemented with a field-programmable gate array (FPGA) is easy to perform using available FPGA design tools. However, it may be difficult to impossible to verify that worst case timing requirements are met for complex asynchronous logic design.
Document ID
20060033325
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Erickson, K.
Date Acquired
August 23, 2013
Publication Date
September 26, 2000
Distribution Limits
Public
Copyright
Other
Keywords
risk FPGA asynchronous

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