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A hierarchical, automated target recognition algorithm for a parallel analog processorA hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.
Document ID
20060035179
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
hdl:2014/22063
Authors
Woodward, Gail
Padgett, Curtis
Date Acquired
August 23, 2013
Publication Date
July 10, 1997
Distribution Limits
Public
Copyright
Other
Keywords
algorithm analog processor eigenvector

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