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Single Event Upset Behavior of CMOS Static RAM CellsAn improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.
Document ID
20060039117
Acquisition Source
Jet Propulsion Laboratory
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Lieneweg, Udo
Jeppson, Kjell O.
Buehler, Martin G.
Date Acquired
August 23, 2013
Publication Date
June 9, 1993
Publication Information
Publication: IEEE Trans. Electron Devices
Subject Category
Electronics And Electrical Engineering
Distribution Limits
Public
Copyright
Other

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