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Single event upset suspectibility testing of the Xilinx Virtex II FPGAHeavy ion testing of the Xilinx Virtex II was conducted on the configuration, block RAM and user flip flop cells to determine their static single-event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA was used to reveal L1/e, values (the LET at which the cross section is l/e times the saturation cross-section) and single-event functional-interrupt failures.
Document ID
20060042524
Acquisition Source
Jet Propulsion Laboratory
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Carmichael, C.
Swift, C.
Yui, G.
Date Acquired
August 23, 2013
Publication Date
January 1, 2002
Publication Information
Publication: AIAA Journal of Spacecraft and Rockets: MAPLD
Subject Category
Electronics And Electrical Engineering
Distribution Limits
Public
Copyright
Other
Keywords
FPGA Virtex II SEU

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