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On-board fault-tolerant SAR processor for spaceborne imaging radar systemsA real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.
Document ID
20060044226
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Fang, Wai-Chi
Le, Charles
Taft, Stephanie
Date Acquired
August 23, 2013
Publication Date
May 21, 2005
Subject Category
Communications And Radar
Meeting Information
Meeting: IEEE International Symposium on Circuits and Systems
Start Date: May 21, 2005
End Date: May 24, 2005
Distribution Limits
Public
Copyright
Other
Keywords
imaging Radar
synthetic aperture radar (SAR)
FPGA
fault tolerant processor

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