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Large CMOS imager using hadamard transform based multiplexingWe have developed a concept design for a large (~10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be ~100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.
Document ID
20060044388
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Karasik, Boris S.
Wadsworth, Mark V.
Date Acquired
August 23, 2013
Publication Date
March 28, 2005
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: International Society for Optical Engineering (SPIE) Defense and Security Symposium
Location: Orlando, FL
Country: United States
Start Date: March 28, 2005
End Date: April 1, 2005
Distribution Limits
Public
Copyright
Other
Keywords
CMOS imager
code-division multiplexing
Hadamard transform

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