NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate ArraysShown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.
Document ID
20060050761
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Swift, Gary M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Allen, Gregory S.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Farmanesh, Farhad
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
George, Jeffrey
(Aerospace Corp. United States)
Petrick, David J.
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Chayab, Fayez
(MDRobotics United States)
Date Acquired
August 23, 2013
Publication Date
January 1, 2006
Subject Category
Computer Programming And Software
Meeting Information
Meeting: Nuclear and Space Radiation Effects Conference
Location: Ponte Vedra Beach, FL
Country: United States
Start Date: July 17, 2006
End Date: July 21, 2006
Distribution Limits
Public
Copyright
Other
Keywords
radiation effects
processors
single event effects
Field Programmable Gate Arrays (FPGA)
upsets

Available Downloads

There are no available downloads for this record.
No Preview Available