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A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace ApplicationsField Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).
Document ID
20090007564
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Roosta, Ramin
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Wang, Xinchen
(Ixia Communications Calabasas, CA, United States)
Sadigursky, Michael
(California State Univ. Northridge, CA, United States)
Tracton, Phil
(California State Univ. Northridge, CA, United States)
Date Acquired
August 24, 2013
Publication Date
September 8, 2004
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: 7th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD)
Location: Washington, DC
Country: United States
Start Date: September 8, 2004
End Date: September 11, 2004
Distribution Limits
Public
Copyright
Other
Keywords
Field Programmable Gate Arrays (FPGA)
dynamic burn in

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