Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
Authors
White, Mark (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States) Vu, Duc (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States) Nguyen, Duc (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States) Ruiz, Ron (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States) Chen, Yuan (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States) Bernstein, Joseph B. (Maryland Univ. College Park, MD, United States) Date Acquired
August 24, 2013
Publication Date
October 16, 2006
Publication Information
Publication: 2006 International Integrated Reliability Workshop Final Report
Publisher: Institute of Electrical and Electronics Engineers
Subject Category
Electronics And Electrical Engineering Meeting Information
Meeting: 2006 International Integrated Reliability Workshop (Poster Presentation)
Country: United States
Start Date: October 16, 2006
End Date: September 19, 2006
Distribution Limits
Public
Keywords
CMOS integrated circuitsaccelerated stress testingadvanced technologyfailure analysis