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Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart PayloadsAccurate, on-board classification of instrument data is used to increase science return by autonomously identifying regions of interest for priority transmission or generating summary products to conserve transmission bandwidth. Due to on-board processing constraints, such classification has been limited to using the simplest functions on a small subset of the full instrument data. FPGA co-processor designs for SVM1 classifiers will lead to significant improvement in on-board classification capability and accuracy.
Document ID
20110007179
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/41707
Authors
Pingree, Paula J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Scharenbroich, Lucas J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Werne, Thomas A. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hartzell, Christine (Georgia Inst. of Tech. Atlanta, GA, United States)
Date Acquired
August 25, 2013
Publication Date
March 6, 2008
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
IEEEAC Paper 1230
Meeting Information
Meeting: IEEE Aerospace Conference
Location: Big Sky, MT
Country: United States
Start Date: March 6, 2008
Sponsors: Institute of Electrical and Electronics Engineers
Distribution Limits
Public
Copyright
Other
Keywords
co-processor
Virtex-4
SVM
classification
FPGA
Xilinx

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