Clock and reset synchronization of high-integrity lockstep self-checking pairs

An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at the respective each module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at the respective each module, indicate to the respective other module that the respective each module is ready to exit the reset mode and exit the reset mode when the respective other module has also indicated that the respective other module is ready to exit the reset mode.