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Initial SEE Testing of MaestroWe have reported on initial SEE sensitivity of the full 49-core Maestro device. Supporting the low-level structures and qualitative system observation goals of phase 1 of testing. Observed sensitivities found to be consistent with Boeing predictions. Highlighted by the L1 data cache sensitivity which drives the rates on the current Maestro device. Presented details to the hardware and software setups that show where the limitations - highlighting future work. Key future work includes testing with memory and IO ports.
Document ID
20130009481
Acquisition Source
Jet Propulsion Laboratory
Document Type
Presentation
External Source(s)
hdl:2014/42682
Authors
Guertin, Steven M. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 27, 2013
Publication Date
May 30, 2012
Subject Category
Computer Programming And Software
Meeting Information
Meeting: Fifth Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies
Location: Albuquerque, NM
Country: United States
Start Date: May 29, 2012
End Date: June 1, 2012
Distribution Limits
Public
Copyright
Other
Keywords
cache sensitivity
single-event effects (SEE)
fault tolerance
manycore microprocessor
radiation effects
multicore microprocessor
Single Event Latchup (SEL)

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