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Single Event Effects in FPGA Devices 2015-2016This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
Document ID
20160009479
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, Melanie
(ASRC Federal Space and Defense Greenbelt, MD, United States)
LaBel, Kenneth
(NASA Goddard Space Flight Center Greenbelt, MD United States)
Pellish, Jonathan
(NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
July 28, 2016
Publication Date
June 13, 2016
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN33310
2015-561-NEPP
Meeting Information
Meeting: 2016 NEPP Electronics Technology Workshop (ETW)
Location: Greenbelt, MD
Country: United States
Start Date: June 13, 2016
End Date: June 16, 2016
Sponsors: NASA Goddard Space Flight Center
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Single Event Upset (SEU) Testing
Xilinx Kintex-7
Xilinx V5
Single event latch-up (SEL)
Single event upset (SEU)
Virtex-5QV
Field Programmable Gate Array (FPGA)
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