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The digital implementation of control compensators: The coefficient wordlength issueThere exists a number of mathematical procedures for designing discrete-time compensators. However, the digital implementation of these designs, with a microprocessor for example, has not received nearly as thorough an investigation. The finite-precision nature of the digital hardware makes it necessary to choose an algorithm (computational structure) that will perform 'well-enough' with regard to the initial objectives of the design. This paper describes a procedure for estimating the required fixed-point coefficient wordlength for any given computational structure for the implementation of a single-input single-output LOG design. The results are compared to the actual number of bits necessary to achieve a specified performance index.
Document ID
19790012582
Document Type
Contractor Report (CR)
Authors
Moroney, P. (Massachusetts Inst. of Tech. Cambridge, MA, United States)
Willsky, A. S. (Massachusetts Inst. of Tech. Cambridge, MA, United States)
Houpt, P. K. (Massachusetts Inst. of Tech. Cambridge, MA, United States)
Date Acquired
September 3, 2013
Publication Date
April 1, 1979
Subject Category
COMPUTER OPERATIONS AND HARDWARE
Report/Patent Number
LIDS-P-897
NASA-CR-158445
Funding Number(s)
CONTRACT_GRANT: NGL-22-009-124
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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