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SUMC fault tolerant computer systemThe results of the trade studies are presented. These trades cover: establishing the basic configuration, establishing the CPU/memory configuration, establishing an approach to crosstrapping interfaces, defining the requirements of the redundancy management unit (RMU), establishing a spare plane switching strategy for the fault-tolerant memory (FTM), and identifying the most cost effective way of extending the memory addressing capability beyond the 64 K-bytes (K=1024) of SUMC-II B. The results of the design are compiled in Contract End Item (CEI) Specification for the NASA Standard Spacecraft Computer II (NSSC-II), IBM 7934507. The implementation of the FTM and memory address expansion.
Document ID
19800025603
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Date Acquired
September 4, 2013
Publication Date
September 10, 1980
Subject Category
Computer Operations And Hardware
Report/Patent Number
NASA-CR-161581
Report Number: NASA-CR-161581
Accession Number
80N34111
Funding Number(s)
CONTRACT_GRANT: NAS8-31747
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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