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BLITZEN: A highly integrated massively parallel machineThe architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.
Document ID
19900007137
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Blevins, D. W. (Microelectronics Center of North Carolina Research Triangle Park., United States)
Davis, E. W. (North Carolina State Univ. Raleigh., United States)
Heaton, R. A. (Microelectronics Center of North Carolina Research Triangle Park., United States)
Reif, J. H. (Duke Univ. Durham, NC., United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1988
Publication Information
Publication: NASA, Goddard Space Flight Center, The 2nd Symposium on the Frontiers of Massively Parallel Computations
Subject Category
Computer Systems
Accession Number
90N16453
Funding Number(s)
CONTRACT_GRANT: DAAL03-88-K-0195
CONTRACT_GRANT: NAG5-966
CONTRACT_GRANT: N00014-88-K-0458
CONTRACT_GRANT: N00014-87-K-0310
CONTRACT_GRANT: N00014-80-C-0647
CONTRACT_GRANT: AF-AFOSR-0386-87
CONTRACT_GRANT: NSF CCR-86-96134
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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