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A VLSI design for a systolic Viterbi decoderA systolic Viterbi decoder for convolutional codes is developed. This decoder uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.
Document ID
19900012583
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Truong, T. K. (Jet Propulsion Lab. California Inst. of Tech., Pasadena., United States)
Satorius, E. (Jet Propulsion Lab. California Inst. of Tech., Pasadena., United States)
Shih, M. T. (University of Southern California Engineering Center Los Angeles., United States)
Reed, I. S. (University of Southern California Los Angeles., United States)
Date Acquired
September 6, 2013
Publication Date
February 15, 1990
Publication Information
Publication: The Telecommunications and Data Acquisition Report
Subject Category
Communications And Radar
Accession Number
90N21899
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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