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First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated CircuitsA separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.
Document ID
Document Type
Conference Paper
Neudeck, Philip G.
(NASA Glenn Research Center Cleveland, OH United States)
Spry, David J.
(NASA Glenn Research Center Cleveland, OH United States)
Chen, Liang-Yu
(Ohio Aerospace Inst. Cleveland, OH, United States)
Date Acquired
December 29, 2016
Publication Date
May 10, 2016
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Meeting Information
Meeting: High Temperature Electronics (HiTEC 2016)
Location: Albuquerque, NM
Country: United States
Start Date: May 10, 2016
End Date: May 12, 2016
Sponsors: International Microelectronics Assembly and Packaging Society (iMAPS)
Funding Number(s)
WBS: WBS 109492.
Distribution Limits
Public Use Permitted.
integrated circuits
silicon carbides
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