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New Developments in Error Detection and Correction Strategies for Critical ApplicationsThe presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different Field programmable gate array (FPGA) device types.
Document ID
20170004736
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, Melanie (ASRC Federal Space and Defense Greenbelt, MD, United States)
Label, Ken (NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
May 25, 2017
Publication Date
May 22, 2017
Subject Category
Electronics And Electrical Engineering
Quality Assurance And Reliability
Report/Patent Number
GSFC-E-DAA-TN42793
Meeting Information
Meeting: Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop
Location: La Jolla, CA
Country: United States
Start Date: May 22, 2017
End Date: May 25, 2017
Sponsors: NASA Headquarters
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Triple modular redundancy (TMR)
Error detection and correction (EDAC)
Field programmable gate array (FPGA); Single Event Effects (SEEs); Mitigation; T
Field programmable gate array (FPGA)
Single Event Effects (SEEs)

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