Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.