A slope reversal video processor having amplitude and pulse width discrimination.

A timing discriminator whose output is relatively insensitive to input pulse width and amplitude is described. The video-handling technique is known as slope reversal processing and is based on tapped delay line estimation methods. The concept, design, breadboard construction, and preliminary laboratory test results are reviewed. The processor system features (1) a peak input voltage dynamic range of 80x starting at 100 microvolts; (2) a four stage preamplifier/line-driver having a voltage gain of 2400x; (3) a tapped delay-line estimator implemented for slope reversal triggering by differential comparison; (4) a nominal plus or minus 2.5 nsec shift of the output trigger leading edge over the entire input voltage range, (5) up to 7 dB discrimination against pulse widths less than 35 nsec; and (6) up to one order of magnitude reduction in the false alarm rate compared to a constant fraction system.