Pulse code modulated signal synchronizer

A bit synchronizer for a split phase PCM transmission is reported that includes three loop circuits which receive incoming phase coded PCM signals. In the first loop, called a Q-loop, a generated, phase coded, PCM signal is multiplied with the incoming signals, and the frequency and phase of the generated signal are nulled to that of the incoming subcarrier signal. In the second loop, called a B-loop, a circuit multiplies a generated signal with incoming signals to null the phase of the generated signal in a bit phase locked relationship to the incoming signal. In a third loop, called the I-loop, a phase coded PCM signal is multiplied with the incoming signals for decoding the bit information from the PCM signal. A counter means is used for timing of the generated signals and timing of sample intervals for each bit period.