A synchronous binary array divider

An asynchronous binary divider formed of an array of identical logic cells is described. Each cell includes a single bit binary subtractor and a selection gate. The array is connected to divisor, dividend, quotient and remainder registers. Divisor and dividend numbers are read into the divisor and dividend registers, respectively. The array of identical logic cells performs the division in parallel asynchronously and places the results of the division in the quotient and remainder registers for subsequent readout.