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Computer interface systemAn interface logic circuit permitting the transfer of information between two computers having asynchronous clocks is disclosed. The information transfer involves utilization of control signals (including request, return-response, ready) to generate properly timed data strobe signals. Noise problems are avoided because each control signal, upon receipt, is verified by at least two clock pulses at the receiving computer. If control signals are verified, a data strobe pulse is generated to accomplish a data transfer. Once initiated, the data strobe signal is properly completed independently of signal disturbances in the control signal initiating the data strobe signal. Completion of the data strobe signal is announced by automatic turn-off of a return-response control signal.
Document ID
19770005778
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Anderson, T. O.
(JPL)
Date Acquired
August 8, 2013
Publication Date
October 26, 1976
Subject Category
Computer Operations And Hardware
Report/Patent Number
Patent Number: NASA-CASE-NPO-13428-1
Patent Number: NASA-CASE-NPO-13447-1
Patent Application Number: US-PATENT-APPL-SN-495022
Patent Number: US-PATENT-3,988,716
Accession Number
77N12721
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-NPO-13428-1|NASA-CASE-NPO-13447-1|US-PATENT-3,988,716
Patent Application
US-PATENT-APPL-SN-495022
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