A parylene coating process for hybrid circuits

The parylene coating process developed during this program consists of (1) obtaining a hybrid cover with a hole in it, (2) sealing of the circuit with a hole in the cover, (3) parylene coating through the hole with the external leads protected from parylene by appropriate fixturing, and (4) sealing of the hole by soldering a pretinned kovar tab. Development of the above process required optimization of the parylene coater parameters to obtain a uniform consistent coating which could offer adequate protection to the circuits, fixture design for packages of various types, determination of the size of the deposition hole, and the amount of dimer charge per run, a process to hermetically seal the deposition holes and establishment of quality control techniques or acceptance criteria for the deposited film.