Strobe-margin test for plated memory systems

Technique measures performance of plated-wire memories. Strobe-margin test (SMT) utilizes worst-case testing and automatically gives exact strobe margin. Test is automatic; thus, memory system-level test is superior to tests at component level that use artificial test conditions. Test is significant tool in design and test of plated-wire memory systems. It can rapidly quantify memory-system margin on each production unit and impact of any design changes.