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FPLA mechanization of arithmetic elements to produce A + B or to pass A onlyA 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.
Document ID
19780024207
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Wallis, D. E. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Taylor, H. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Rubin, A. L. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 9, 2013
Publication Date
August 15, 1978
Publication Information
Publication: The Deep Space Network
Subject Category
Numerical Analysis
Accession Number
78N32150
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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