NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Press Enter or click the Search button to begin your search.

Back to Results
Array automated assembly task, phase 2. Low cost silicon solar array projectSeveral modifications instituted in the wafer surface preparation process served to significantly reduce the process cost to 1.55 cents per peak watt in 1975 cents. Performance verification tests of a laser scanning system showed a limited capability to detect hidden cracks or defects, but with potential equipment modifications this cost effective system could be rendered suitable for applications. Installation of electroless nickel plating system was completed along with an optimization of the wafer plating process. The solder coating and flux removal process verification test was completed. An optimum temperature range of 500-550 C was found to produce uniform solder coating with the restriction that a modified dipping procedure is utilized. Finally, the construction of the spray-on dopant equipment was completed.
Document ID
19790006381
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Rhee, S. S.
(Sensor Technology, Inc. Chatsworth, CA, United States)
Jones, G. T.
(Sensor Technology, Inc. Chatsworth, CA, United States)
Allison, K. T.
(Sensor Technology, Inc. Chatsworth, CA, United States)
Date Acquired
September 3, 2013
Publication Date
September 30, 1978
Subject Category
Energy Production And Conversion
Report/Patent Number
DOE/JPL-954865-78/4
NASA-CR-158044
QTR-4
Report Number: DOE/JPL-954865-78/4
Report Number: NASA-CR-158044
Report Number: QTR-4
Accession Number
79N14552
Funding Number(s)
CONTRACT_GRANT: JPL-954865
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
No Preview Available