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Digital data reformatter/deserializerA method and apparatus is presented for reformatting and de-serializing a serially-received sequence of data words, each consisting of a fixed number of binary data bits. A block of nm bits is serially fed into a shift register or serially-connected group of shift registers. In lieu of the(nm-1)th shifts, the bits are rearranged within the shift register in parallel fashion, according to a prescribed scheme. Shifting then continues, until the first bit of each data word appears in the last bit position in the shift register, at which time that data word is shifted in parallel into an output buffer stage, from which it is outputted in parallel, after a fixed delay.
Document ID
19790012580
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Engel, A.
(JPL)
Springer, L. R.
(JPL)
Date Acquired
September 3, 2013
Publication Date
February 13, 1979
Subject Category
Computer Operations And Hardware
Report/Patent Number
Patent Number: US-PATENT-4,139,839
Patent Application Number: US-PATENT-APPL-SN-779415
Patent Number: NASA-CASE-NPO-13676-1
Accession Number
79N20751
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-4,139,839|NASA-CASE-NPO-13676-1
Patent Application
US-PATENT-APPL-SN-779415
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