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C-MOS bulk metal design handbookThe LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.
Document ID
19790022304
Acquisition Source
Legacy CDMS
Document Type
Technical Memorandum (TM)
Authors
Edge, T. M.
(NASA Marshall Space Flight Center Huntsville, AL, United States)
Date Acquired
September 3, 2013
Publication Date
July 1, 1977
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NASA-TM-78126
Report Number: NASA-TM-78126
Accession Number
79N30475
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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