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Independent synchronizer for digital decodersLogic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.
Document ID
19800000004
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Stiffler, J. J. (Raytheon Co.)
Date Acquired
August 10, 2013
Publication Date
August 1, 1980
Publication Information
Publication: NASA Tech Briefs
Volume: 5
Issue: 1
ISSN: 0145-319X
Subject Category
Electronic Components And Circuits
Report/Patent Number
MSC-16723
ISSN: 0145-319X
Report Number: MSC-16723
Accession Number
80B10004
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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