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The automated array assembly task of the low-cost silicon solar array project, phase 2Several specific processing steps as part of a total process sequence for manufacturing silicon solar cells were studied. Ion implantation was identified as the preferred process step for impurity doping. Unanalyzed beam ion implantation was shown to have major cost advantages over analyzed beam implantation. Further, high quality cells were fabricated using a high current unanalyzed beam. Mechanically masked plasma patterning of silicon nitride was shown to be capable of forming fine lines on silicon surfaces with spacings between mask and substrate as great as 250 micrometers. Extensive work was performed on advances in plated metallization. The need for the thick electroless palladium layer was eliminated. Further, copper was successfully utilized as a conductor layer utilizing nickel as a barrier to copper diffusion into the silicon. Plasma etching of silicon for texturing and saw damage removal was shown technically feasible but not cost effective compared to wet chemical etching techniques.
Document ID
19810008060
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Coleman, M. G.
(Motorola, Inc. Phoenix, AZ, United States)
Pryor, R. A.
(Motorola, Inc. Phoenix, AZ, United States)
Sparks, T. G.
(Motorola, Inc. Phoenix, AZ, United States)
Legge, R.
(Motorola, Inc. Phoenix, AZ, United States)
Saltzman, D. L.
(Motorola, Inc. Phoenix, AZ, United States)
Date Acquired
September 4, 2013
Publication Date
January 1, 1980
Subject Category
Energy Production And Conversion
Report/Patent Number
DOE/JPL-954847-80/8
NASA-CR-163880
JPL-9950-456
MOTOROLA-2345/8
Report Number: DOE/JPL-954847-80/8
Report Number: NASA-CR-163880
Report Number: JPL-9950-456
Report Number: MOTOROLA-2345/8
Accession Number
81N16577
Funding Number(s)
CONTRACT_GRANT: JPL-954847
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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