NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Press Enter or click the Search button to begin your search.

Back to Results
Decommutator patchboard verifierA system for automatically verifying the connections between terminals of a patchboard is described. The system includes a back plane having a plurality of plugs corresponding to the pins of the patchboard. A number of decoders are connected to the plugs of the back plane so that a signal can be sequentially applied to each plug of the back plane under control of a stepping register and a control circuit. A plurality of data selectors are also connected to the plugs of the back plane and under control of a second external register. This control circuit sequentially makes connections between an output circuit and the plugs of the back plane so as to patch the signal applied to a respective plug through a patch connection to the output circuit. The precise locations of the patches on the patchboard can be identified and compared with previously stored information in a memory unit.
Document ID
19810017822
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Brunson, J. W.
(NASA John F. Kennedy Space Center Cocoa Beach, FL, United States)
Date Acquired
August 11, 2013
Publication Date
May 12, 1981
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Number: NASA-CASE-KSC-11065-1
Patent Application Number: US-PATENT-APPL-SN-051271
Patent Number: US-PATENT-4,267,594
Accession Number
81N26359
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-KSC-11065-1|US-PATENT-4,267,594
Patent Application
US-PATENT-APPL-SN-051271
No Preview Available