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Method of making V-MOS field effect transistors utilizing a two-step anisotropic etching and ion implantationA method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.
Document ID
19810017823
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Jhabvala, M. D.
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Date Acquired
August 11, 2013
Publication Date
June 9, 1981
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Number: NASA-CASE-GSC-12515-1
Patent Application Number: US-PATENT-APPL-SN-172727
Patent Number: US-PATENT-4,272,302
Accession Number
81N26360
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-GSC-12515-1|US-PATENT-4,272,302
Patent Application
US-PATENT-APPL-SN-172727
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