PN lock indicator for dithered PN code tracking loop

In a delay-lock one-delta (+or - 1/2 chip) dithered PN code tracking loop, an indication of lock in the PN code tracking loop is provided by delaying the dithered local PN code by a half chip to produce a +0, -1 dithered PN code that is then multiplied with the received PN-spread IF signal to produce a signal proportional to the correlation of this dithered code offset from the received code. The correlation signal is bandpass filtered, amplified with AGC control, and square-law detected to obtain a dc signal proportional to the degree of correlation. The dc signal is multiplied by the dithering control signal to effectivity substract noise voltage from the lock correlation signal which is then compared with a PN lock status signal.