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Chip level simulation of fault tolerant computersChip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault tolerant computer was modeled. An efficient approach to functional fault simulation was developed. Simulation software was also developed.
Document ID
19820022029
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Armstrong, J. R. (Virginia Polytechnic Inst. and State Univ. Blacksburg, VA, United States)
Date Acquired
September 4, 2013
Publication Date
May 31, 1982
Subject Category
Computer Operations And Hardware
Report/Patent Number
NAS 1.26:169154
NASA-CR-169154
Report Number: NAS 1.26:169154
Report Number: NASA-CR-169154
Accession Number
82N29905
Funding Number(s)
CONTRACT_GRANT: NAG1-174
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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