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The VLSI design of a Reed-Solomon encoder using Berlekamps bit-serial multiplier algorithmRealization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes ofter requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.
Document ID
19820024661
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Truong, T. K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reed, I. S. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hsu, I. S. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Wang, K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Yeh, C. S. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 10, 2013
Publication Date
August 15, 1982
Publication Information
Publication: The Telecommun. and Data Acquisition Report
Subject Category
Numerical Analysis
Accession Number
82N32537
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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