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The VLSI design of a single chip Reed-Solomon encoderA design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.
Document ID
19830006722
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Truong, T. K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reed, I. S. (Univ. of Southern California)
Date Acquired
September 4, 2013
Publication Date
November 15, 1982
Subject Category
Numerical Analysis
Report/Patent Number
JPL-PUB-82-84
NASA-CR-169663
NAS 1.26:169663
Report Number: JPL-PUB-82-84
Report Number: NASA-CR-169663
Report Number: NAS 1.26:169663
Accession Number
83N14993
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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