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Chip level simulation of fault tolerant computersChip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed.
Document ID
19830026325
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Armstrong, J. R. (Virginia Polytechnic Inst. and State Univ. Blacksburg, VA, United States)
Date Acquired
September 4, 2013
Publication Date
January 1, 1983
Subject Category
Computer Operations And Hardware
Report/Patent Number
NASA-CR-173027
NAS 1.26:173027
Report Number: NASA-CR-173027
Report Number: NAS 1.26:173027
Accession Number
83N34596
Funding Number(s)
CONTRACT_GRANT: NAG1-174
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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