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Validation of a fault-tolerant clock synchronization systemA validation method for the synchronization subsystem of a fault tolerant computer system is investigated. The method combines formal design verification with experimental testing. The design proof reduces the correctness of the clock synchronization system to the correctness of a set of axioms which are experimentally validated. Since the reliability requirements are often extreme, requiring the estimation of extremely large quantiles, an asymptotic approach to estimation in the tail of a distribution is employed.
Document ID
19840026127
Acquisition Source
Legacy CDMS
Document Type
Technical Publication (TP)
Authors
Butler, R. W. (NASA Langley Research Center Hampton, VA, United States)
Johnson, S. C. (NASA Langley Research Center Hampton, VA, United States)
Date Acquired
September 4, 2013
Publication Date
September 1, 1984
Subject Category
Computer Systems
Report/Patent Number
L-15799
NASA-TP-2346
NAS 1.60:2346
Report Number: L-15799
Report Number: NASA-TP-2346
Report Number: NAS 1.60:2346
Accession Number
84N34198
Funding Number(s)
PROJECT: RTOP 505-34-13
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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