Fast Control Sequencer

Unit faster than conventional circuits and contains fewer integrated circuits. Fast logic controller accommodates three delays before second half cycle of clock signal strobes status latch: Outputs of pipeline register must settle; selected input status line signal must propagate through status multiplexer and arrive at status latch; and it takes 3 nanoseconds for status latch set up before strobed. During second half cycle, output-enable line produces next instruction and applies it to pipeline register.