Fast VLSI Viterbi Decoder

Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.