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A summary of JPL single event upset test data from May 1982, through January 1984A summary of single event upset data for 42 device types (including RAMs, 4-bit slices, microprocessors, 4-bit counters, and flip-flops) studied at 11 different accelerator tests (performed chiefly with the Berkeley 88-inch cyclotron and the Cal Tech Van de Graaff) is presented. All bipolar and NMOS RAMs were found to be SEU sensitive, some with very low LET thresholds. Some CMOS or CMOS/SOS RAMs were hard; and the CMOS microprocessors were hard, but the bipolar and NMOS microprocessors were soft. Several devices were found to exhibit a cross section that depends strongly on LET, even when the LET is well above the LET threshold. A ranking of hardness is presented for the logic devices tested.
Document ID
19850036411
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Nichols, D. K.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Price, W. E.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Malone, C. J.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Smith, L. S.
(California Institute of Technology, Jet Propulsion Laboratory, Pasadena CA, United States)
Date Acquired
August 12, 2013
Publication Date
December 1, 1984
Publication Information
Publication: IEEE Transactions on Nuclear Science
Volume: NS-31
ISSN: 0018-9499
Subject Category
Nuclear And High-Energy Physics
Accession Number
85A18562
Distribution Limits
Public
Copyright
Other

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