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The development of an interim generalized gate logic software simulatorA proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
Document ID
19860010477
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Mcgough, J. G. (Allied Bendix Aerospace Teterboro, NJ, United States)
Nemeroff, S. (Allied Bendix Aerospace Teterboro, NJ, United States)
Date Acquired
September 5, 2013
Publication Date
December 1, 1985
Subject Category
Mathematical And Computer Sciences (General)
Report/Patent Number
NAS 1.26:177939
NASA-CR-177939
Report Number: NAS 1.26:177939
Report Number: NASA-CR-177939
Accession Number
86N19948
Funding Number(s)
CONTRACT_GRANT: NAS1-15946
PROJECT: RTOP 505-34-13-30
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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