NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
The hypercluster: A parallel processing test-bed architecture for computational mechanics applicationsThe development of numerical methods and software tools for parallel processors can be aided through the use of a hardware test-bed. The test-bed architecture must be flexible enough to support investigations into architecture-algorithm interactions. One way to implement a test-bed is to use a commercial parallel processor. Unfortunately, most commercial parallel processors are fixed in their interconnection and/or processor architecture. In this paper, we describe a modified n cube architecture, called the hypercluster, which is a superset of many other processor and interconnection architectures. The hypercluster is intended to support research into parallel processing of computational fluid and structural mechanics problems which may require a number of different architectural configurations. An example of how a typical partial differential equation solution algorithm maps on to the hypercluster is given.
Document ID
19870011334
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Blech, Richard A.
(NASA Lewis Research Center Cleveland, OH, United States)
Date Acquired
September 5, 2013
Publication Date
January 1, 1987
Subject Category
Computer Systems
Report/Patent Number
NASA-TM-89823
E-3469
NAS 1.15:89823
Report Number: NASA-TM-89823
Report Number: E-3469
Report Number: NAS 1.15:89823
Accession Number
87N20767
Funding Number(s)
PROJECT: RTOP 505-62-21
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
No Preview Available