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A VLSI single chip (255,223) Reed-Solomon encoder with interleaverA single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp.
Document ID
19870014399
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Hsu, I. S.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reed, I. S.
(University of Southern California Los Angeles., United States)
Date Acquired
September 5, 2013
Publication Date
May 15, 1987
Publication Information
Publication: The Telecommunications and Data Acquisition Report
Subject Category
Electronics And Electrical Engineering
Accession Number
87N23832
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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