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The architecture of tomorrow's massively parallel computerGoodyear Aerospace delivered the Massively Parallel Processor (MPP) to NASA/Goddard in May 1983, over three years ago. Ever since then, Goodyear has tried to look in a forward direction. There is always some debate as to which way is forward when it comes to supercomputer architecture. Improvements to the MPP's massively parallel architecture are discussed in the areas of data I/O, memory capacity, connectivity, and indirect (or local) addressing. In I/O, transfer rates up to 640 megabytes per second can be achieved. There are devices that can supply the data and accept it at this rate. The memory capacity can be increased up to 128 megabytes in the ARU and over a gigabyte in the staging memory. For connectivity, there are several different kinds of multistage networks that should be considered.
Document ID
19870017115
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Batcher, Ken
(Goodyear Aerospace Corp. Akron, OH, United States)
Date Acquired
September 5, 2013
Publication Date
July 1, 1987
Publication Information
Publication: NASA. Goddard Space Flight Center, Frontiers of Massively Parallel Scientific Computation
Subject Category
Computer Operations And Hardware
Accession Number
87N26548
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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