A simulation-based fault injection experiment to evaluate self-test diagnostics for a fault-tolerant computer

The design and results of a fault injection experiment conducted in the Airlab facility at NASA-Langley using a logic network simulator are described. An attempt was made to determine the effectiveness of the diagnostic self-test sequences used to detect failures in the communicator/interstage (C/I) of a fault-tolerant processor (FTP). Identification of the undetected faults in the C/I Status Register logic resulted in changes in the diagnostic test sequences implemented for the FTP.