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VLSI high speed packet processorThe Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.
Document ID
19890043666
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Grebowsky, Gerald J.
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Dominy, Carol T.
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1988
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: ITC/USA/''88
Location: Las Vegas, NV
Country: United States
Start Date: October 17, 1988
End Date: October 20, 1988
Accession Number
89A31037
Distribution Limits
Public
Copyright
Other

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