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Method of up-front load balancing for local memory parallel processorsIn a parallel processing computer system with multiple processing units and shared memory, a method is disclosed for uniformly balancing the aggregate computational load in, and utilizing minimal memory by, a network having identical computations to be executed at each connection therein. Read-only and read-write memory are subdivided into a plurality of process sets, which function like artificial processing units. Said plurality of process sets is iteratively merged and reduced to the number of processing units without exceeding the balance load. Said merger is based upon the value of a partition threshold, which is a measure of the memory utilization. The turnaround time and memory savings of the instant method are functions of the number of processing units available and the number of partitions into which the memory is subdivided. Typical results of the preferred embodiment yielded memory savings of from sixty to seventy five percent.
Document ID
19910005456
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Baffes, Paul Thomas
(NASA Lyndon B. Johnson Space Center Houston, TX, United States)
Date Acquired
August 14, 2013
Publication Date
April 24, 1990
Subject Category
Computer Systems
Report/Patent Number
Patent Number: NASA-CASE-MSC-21348-1
Patent Number: US-PATENT-4,920,487
Patent Application Number: US-PATENT-APPL-SN-283106
Accession Number
91N14769
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-MSC-21348-1|US-PATENT-4,920,487
Patent Application
US-PATENT-APPL-SN-283106
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